IEC 62417 pdf download – Semiconductor devices – Mobile ion tests for metal-oxide semiconductor field effect transistors (MOSFETs)

IEC 62417 pdf download – Semiconductor devices – Mobile ion tests for metal-oxide semiconductor field effect transistors (MOSFETs)

IEC 62417 pdf download – Semiconductor devices – Mobile ion tests for metal-oxide semiconductor field effect transistors (MOSFETs)
1 Scope
This present standard provides a wafer level test procedure to determine the amount of positive mobile charge in oxide layers in metal-oxide semiconductor field effect transistors. . It is applicable to both active and parasitic field effect transistors. The mobile charge can cause degradation of microelectronic devices, e.g. by shifting the threshold voltage of MOSFETs or by inversion of the base in bipolar transistors.
2 Abbreviations and letter symbols
This standard uses the following abbreviations and letter symbols:
CV test capacitance-voltage measurement
HFCV test high frequency capacitance-voltage measurement
V g
gate voltage
t ox
oxide thickness
I ds
drain-source current
V dd
positive power supply voltage
V dd,max
maximum supply voltage
V t
transistor threshold voltage
V t,initial
the absolute value of the threshold voltage before the test
V supply
the absolute value of the supply voltage
ε ox
dielectric constant of the oxide
3 General description
The stress applied is on test structures at an elevated temperature where mobile ions can overcome the energy barriers at the interfaces and the ion mobility in the oxide is sufficiently high. Two test methods are described in this document.
• Bias temperature stress (BTS)
• Voltage sweep (VS).
The bias temperature stress test is done on transistors. The threshold voltage is determined from an I ds – V gs measurement at room temperature on fresh structures. The threshold voltage is defined as the gate voltage needed to force a fixed drain current through the transistor. Then, a positive gate stress is applied at a high temperature, to sweep the mobile ions towards the substrate. After the stress the test structure is cooled to room temperature with the bias still applied. A second I ds – V gs curve is measured at room temperature. The sequence is completed with a negative gate stress at high temperature followed by an I ds – V gs measurement at room temperature. Mobile charge causes a shift in the I ds – V gs curve. The distance over which the curve is shifted is a measure of the amount of mobile charge in the insulator.
Edge effects of the transistor structure can be taken into account by applying a negative gate bias for 2 minutes duration at the elevated temperature prior to the BTS measurement.
NOTE Mobile charge in dielectric layers above a large area polysilicon or metal-plate cannot be detected, because there is no electric field which drives the ions towards the underlying oxide. To overcome this problem special edge sensitive test structures can be used, that have a large edge/area value, e.g. structures with fingers. The voltage sweep measurements are done on capacitors. A quasi-static C-V curve is measured and compared with a low-frequency C-V curve. The ionic displacement current, which appears as a peak in the quasi-static C-V curve, is indicative of the mobile ion concentration.
4 Test equipment The hot chuck shall be capable of maintaining a temperature of 250 °C. A capacitance (LCR) meter is needed for HFCV measurements and quasi-static C-V measurements.
A pA-meter is needed for low-frequency C-V (typical frequency = 1 kHz) measurements. The frequency for low-frequency C-V measurements may differ from 1 kHz as long as the accumulation and inversion capacitances differ no more than 1 0 %. 5 Test structures The test structures for bias temperature stress are transistors and, for voltage sweep, capacitors are used. The minimum area A min of this capacitor is calculated from the voltage sweep rate dV/dt and the lowest measurable current I min (determined by the resolution of the test equipment) according to the following equation:
ε 0 is the permittivity of vacuum.
6 Sample size
The recommended sample size is 5.
7 Conditions
The electric field during stress is as follows:
±1 ,0 MV/cm with a minimum of (operating voltage +1 0 %) for gate oxide;
±0,2 MV/cm for polysilicon gates on field oxide;
± 0,3 MV/cm for metal gates on field oxide.
The electric field is calculated as V g /t ox