IEC 62416 pdf download – Semiconductor devices – Hot carrier test on MOS transistors

IEC 62416 pdf download – Semiconductor devices – Hot carrier test on MOS transistors
3 Test structures
For the evaluation of the hot carrier degradation vulnerability of a technology，nominaltransistors (L = Lnominal)are recommended. The following gate lengths are recommendedwhen lifetime extrapolation versus L is needed (see 9.1): L= 1,0 ×LnominalL = 1,5×Lnominal， = 2,0 × Lnominal:i = 5,0× Lnominal，L = w.
Gates and sources of the transistors may be combined to reduce the number of bond padsrequired for these test structures.
Typical values for W are 10 um for Lnominal < 1 um,and 20 um for Lnominal1um. Atransistor with small W (e.g. W =Lnominal)can be used to evaluate the occurrence of potential'narrow width' effects. The nominal transistor shall be placed with various orientations on the wafer (e.g. one withthe orientation of its gate parallel to the flat of the wafer and one with its gate orientationperpendicular to the flat) whenever asymmetry effects due to ion implantation are expected. 4Stress time Typically 40 000 s (one night), in some 'low voltage' cases 200 000 s (1 weekend); readpointslogarithmically spaced (at least 3 per decade). Stress times shall be chosen such that thedegradation exceeds at least 20 % of the maximum value for the selected failure criterion (seeClause 8). 5 Stress conditions At least 3 different Vds.stress conditions where Vds,stress max